a AN-413 APPLICATION NOTE * P.O. ONE TECHNOLOGY WAY * NORWOOD, BOX 9106 MASSACHUSETTS 02062-9106 * 617/329-4700 Evaluation Board for the AD7890, 12-Bit Serial, Data Acquisition System by Albert O'Grady part contains an on-chip control register accessible via the serial port and allows control of channel selection, conversion start, and power down of the part. This flexible serial interface allows the AD7890 to connect directly to digital signal processors (ADSP-2101, TMS320C25, etc.) and microcontrollers (8XC51, 68HC11, etc.). Full data on the AD7890 is available in the AD7890 data sheet available from Analog Devices and should be consulted in conjunction with this application note when using the evaluation board. INTRODUCTION This application note describes the evaluation board for the AD7890 12-bit serial data acquisition system. The AD7890 is an eight-channel 12-bit data acquisition system which operates from a single +5 V supply and contains an input multiplexer, on-chip track-and-hold amplifier, high speed 12-bit ADC, 2.5 V reference and a high speed serial interface. The AD7890 accepts an analog input range of 10 V, 0 to 4.096 V or 0 V to +2.5 V depending on the version of the part being used. The 78L05 IN V+ OUT 2 GND VIN IC6 C3 0.1F SKT 11 C4 10F AD780 CLKIN C14 10F IC7 1/2 74HC4050 DATA OUT 5 CLKIN VDD 2 3 SCLK 8 3 9 TFS IC4 10 RFS 5 5 7 6 3 1 AD7890 C8, C10 10F V+ P O N M SKT 8 L K J I SKT 6 H G F E SKT 4 D SKT 2 C B A SKT 1 SKT 7 VIN 8 VIN 7 2 SKT 5 VIN 6 VIN 5 VIN5 20 12 14 VIN4 19 6 IC5 13 8 10 9 SKT 3 VIN 4 VIN 3 VIN3 18 2 VDD SMODE 7 9 11 12 2 3 1 SCLK 8 B A B 5 7 VIN2 17 1/2 74HC125 6 VIN1 16 VDD 5 CONVST 4 CEXT C16 120pF 6 SKT 10 CONVST 2 LK4 IC5 MUX OUT 13 C6, C12 10F + SHA IN 14 A 3 1 R4 10k VDD SKT 14 12 13 9 LK1 DGND C15 0.1F 14 IC8 DVDD C7, C9 0.1F VIN8 23 R1 10k NC EXT REF A VIN6 21 8 SKT 9 LK2 C 9 4 2 4 IC3 8 1/2 74HC125 NC GND VIN7 22 LK5 RFS + B REFOUT/ 24 REFIN 11 DATA IN VDD R2 10k TFS 6 7 12 10 DATA OUT VDD R3 10k DATA IN 5 4 7 6 6 VOUT LK3 AGND AGND DGND 1 15 3 IC1 2* AD713JN SKT 13 SHA IN SKT 12 MUX OUT Figure 1. Evaluation Board Circuit Diagram C5, C11 0.1F V- VIN 2 VIN 1 LK2 This option is used to select the reference source for the AD7890 REFIN/REFOUT pin. Onboard components include an AD780, a pin programmable +2.5 V or +3 V ultrahigh precision bandgap reference, bus buffers for the serial data lines and input buffer amplifiers to buffer the eight analog inputs. Interfacing to this board is through a 9-way D-type connector. External sockets are provided for the conversion start input, analog inputs, clk in, mux out, sha in and external reference input options. With this link in Position A, the on-chip 2.5 V reference is used as the reference for the AD7890. The output impedance of this reference is 2 k allowing this reference to be overdriven when using an external 2.5 V reference. In Position B, the AD780 2.5 V reference is selected as the reference for the AD7890. In Position C the reference for the part is provided from the external socket SKT9. OPERATING THE AD7893 EVALUATION BOARD Power Supplies This evaluation board has three analog power supply inputs: AVDD, AGND and VSS. These supplies are +15 V, 0 V and -15 V respectively and are used to power the onboard AD713 buffer amplifiers. The +15 V supply is used in conjunction with the LM78L05, a 5 V linear regulator, to provide the VDD for the AD7890 and the VIN for the AD780 voltage reference. There are two digital power supply inputs, DVDD and DGND, that are used to power the digital logic on the board. These supplies can be provided through the D-type connector or through the connection pins labelled on the board. LK3 This link, when in place, connects the MUX OUT to the SHA IN. When this link is removed, the output of the multiplexer appears at the MUX OUT pin and also at MUX OUT (SKT12), and thus the user can insert an antialiasing filter or signal conditioning between the multiplexer and the ADC. The output range from the MUX OUT is 0 V to 2.5 V and the output impedance is 3.5 k. The SHA IN is the input to the on-chip track and hold and is a high impedance input and accepts signals in the range of 0 V to 2.5 V. The SHA IN pin can be driven directly from SKT13 with LK3 removed. All supplies are decoupled to ground with 10 F tantalum and 0.1 F ceramic disc capacitors. The AVDD and VSS supplies are decoupled to the AGND plane while the DVDD supply is decoupled to the DGND plane. LK4 This provides two options on each of the analog input channels. Option one selects the analog input for each channel from the external socket. The second option facilitates the use of the grid for signal conditioning and the signal can be linked to the VIN. The following table describes the options associated with LK4. The evaluation board uses extensive ground planing to minimize any high frequency noise interference from the onboard clocks or any other sources. Once again, the ground planing for the analog section is kept separate from that for the digital section and they are joined only at the AD7890 AGND and DGND pins. Table I. Options Associated with LK4 Shorting Plug Options There are five shorting plug options that must be set before using the evaluation board. These are outlined below: LK1 This is a double link used to configure the bidirectional buffer on the SCLK and RFS inputs to the AD7890. The position of this link also controls the SMODE pin on the AD7890 configuring the part for self-clocking or external clocking mode of operation. In the external clocking mode both links of LK1 must be in Position A, setting the SMODE pin on the AD7890 to a logic high and routing the RFS and SCLK signals from the 9-way D-type connector to the AD7890. In the self-clocking mode both links on LK1 must be in Position B, configuring the SMODE pin on the AD7890 to a logic low and routing the RFS and SCLK output signals from the AD7890 to the 9-way D-type connector. Option Function A B C D E F G H I J K L M N O P Grid to VIN1 via buffer amplifier SKT1 to VIN1 via buffer amplifier Grid to VIN2 via buffer amplifier SKT2 to VIN2 via buffer amplifier Grid to VIN3 via buffer amplifier SKT3 to VIN3 via buffer amplifier Grid to VIN4 via buffer amplifier SKT4 to VIN4 via buffer amplifier Grid to VIN5 via buffer amplifier SKT5 to VIN5 via buffer amplifier Grid to VIN6 via buffer amplifier SKT6 to VIN6 via buffer amplifier Grid to VIN7 via buffer amplifier SKT7 to VIN7 via buffer amplifier Grid to VIN8 via buffer amplifier SKT8 to VIN8 via buffer amplifier LK5 This link in place connects RFS and TFS together and is useful in applications which require that data be transmitted and received at the same time. -2- DVDD EVALUATION BOARD INTERFACING Interfacing to the evaluation board is via a 9-way D-Type connector, SKT14. The pinout for this connector is shown in Figure 2, and its pin designations are given in Table II. Digital +5 V Supply. This line is connected to the DVDD supply line on the evaluation board. It allows the user to provide the digital supply via the connector along with the other digital signals. 1 SKT14 PIN DESCRIPTION SCLK Serial Clock Input/Output. In the external clocking mode (LK1 in Position A) an external serial clock is applied through this input to load data to the control register and to access data from the output register. In the self-clocking mode (LK1 in Position B) the internal serial clock is used to load data to the control register and to access data from the data register. This clock appears at the SCLK pin. The internal serial clock is derived from the master clock. This serial clock is buffered using a 74HC125 three-state buffer on the evaluation board and LK1 determines the direction of this bidirectional buffer depending on the mode of operation. RFS TFS DATA IN DGND 2 6 3 7 4 8 5 9 Figure 2. Pin Configuration for SKT14, D-Type Connector Table II. SKT14 Pin Functions Receive Frame Sync. This can be an input or output depending on the mode of operation. In external clocking mode this pin is used to provide an active low framing pulse to access data from the data register. In the self-clocking mode an active low framing pulse which is internally generated by the part appears at this pin. This RFS signal is buffered on the board using a 74HC125 three-state buffer configured for bidirectional operation using LK1. Pin No. Mnemonic 1 2 3 4 5 6 7 8 9 SCLK N/C RFS TFS DATA IN DGND DATAOUT DVDD N/C SOCKETS There are fourteen sockets relevant to the operation of the AD7890 on this evaluation board. The functions of these sockets are outlined in Table III. Table III. Socket Functions Socket Transmit Frame Sync. This buffered input controls the AD7890 TFS input, and serial data is expected after the falling edge of this signal. There is a 10 k pull-up resistor on this line to pull it to its inactive state if left unconnected. This buffered input pin is used to provide the serial data to be loaded to the control register of the AD7890. Digital Ground. This line is connected to the digital ground plane on the evaluation board. It allows the user to provide the digital supply via the connector along with the other digital signals. DATAOUT Serial Data Output. Serial data from the part is obtained at this output. This data is buffered by 74HC4050 hex buffer before arriving at the DATAOUT pin of the connector. The serial data is clocked out by the rising edge of SCLK and is valid on the falling of SCLK. -3- Function SKT1-SKT8 Subminiature BNC Sockets for the Eight Analog Input Channels SKT9 Subminiature BNC Socket for External Reference SKT10 Subminiature BNC Socket for CONVST Input SKT11 Subminiature BNC Socket for Master Clock Input SKT12 Subminiature BNC Socket for MUX OUT. The output of the on-chip multiplexer appears at this pin. SKT13 Subminiature BNC Socket for the SHA IN Pin. An input to the on-chip track/hold can be applied to this socket. SKT14 9-Way D-Type Connector SET-UP CONDITIONS Care should be taken before applying power and signals to the evaluation board to ensure that all link positions are as per the required operating mode. Figure 5 shows the silkscreen layout of the board in order to ease setup. The following are the required link positions for the two modes of operation. Software conversion starts are initiated by writing a logic 1 to the CONV bit of the control register. The internal pulse and the conversion process are initiated after the sixth serial clock cycle of the write cycle if a 1 is written to the CONV bit. With a 1 in the CONV bit the external CONVST input is disabled. Writing a 0 to the CONV bit in the control register enables the external convert start. External Clocking Mode LK1 Both links in Position A configuring both SCLK and RFS as inputs. External Clocking Mode The AD7890 is configured for its external clocking mode by tying the SMODE pin of the device to a logic high (LK1 on evaluation board in Position A). In this mode, SCLK and RFS of the AD7890 are configured as inputs. This external clocking mode is designed for direct interface to systems which provide a serial clock output which is synchronized to the serial data output including microcontrollers such as the 80C51, 87C51, 68HC11 and 68HC05 and most digital signal processors. Figure 3 shows a timing and control sequence required to obtain optimum performance from the part in external clocking mode. LK2 This link selects the reference input and can be placed in any of the 3 positions. A-internal reference, B-AD780, C-external reference from SKT9. LK3 This should be in place connecting MUX OUT to SHA IN. LK4 There should be a link inserted in each of the following positions to connect the analog inputs from SKT1 to SKT8 to their respective input, B, D, F, H, J, L, N and P. In the sequence shown in Figure 3, conversion is initiated on the rising edge of CONVST, and new data is available in the output register of the AD7890 5.9 s later. Once the read operation has taken place, a further 500 ns should be allowed before the next rising edge of CONVST to optimize the settling of the track/hold before the next conversion is initiated. The diagram shows the read operation and the write operation taking place in parallel. On the sixth falling edge of SCLK in the write sequence, the internal pulse will be initiated. Assuming MUX OUT is connected to SHA IN, 2 s are required between this sixth falling edge of SCLK and the rising edge of CONVST to allow for the full acquisition time of the track/hold amplifier. With the serial clock rate at its maximum of 10 MHz, the achievable throughput rate for the part is 5.9 s (conversion time) plus 0.6 s (six serial clock pulses before internal pulse is initiated) plus 2 s (acquisition time). This results in a minimum throughput time of 8.5 s (equivalent to a throughput rate of 117 kHz). If the part is operated with a slower serial clock, it will impact the achievable throughput rate. LK5 This link is put in place for applications that require data to be transmitted and received at the same time, i.e., it ties TFS and RFS together. If this facility is not required then the link is omitted. Internal Clocking Mode LK1 Both links in Position B configuring both SCLK and RFS as outputs. All other links can be configured as for the external clocking mode described above. CONTROLLING THE AD7890 There are two modes (external clocking and selfclocking) of operation applicable to the AD7890 and are selected by the SMODE pin which is controlled from LK1 on the evaluation board. Channel selection is controlled through a 5-bit control register which is accessible through the serial port (SKT14). This control register contains three bits for channel address, a software conversion start bit and a bit to put the part into sleep mode. There are two methods of initiating a conversion on the AD7890, the software conversion start and a hardware conversion start which can be applied through the conversion start input (SKT10). A rising edge on this CONVST input puts the track/hold into hold mode and a conversion is initiated. The conversion time for the part is determined from the clock signal applied to CLK IN (SKT11) on the board. With a 2.5 MHz master clock, conversion time for the AD7890 is 5.9 s from the rising edge of the CONVST signal. 2 s is required for track/ hold acquisition time. An internal pulse is generated and appears on CEXT whenever a multiplexer address is loaded to the AD7890 control register, and its duration will depend on the value of CEXT used. In applications where the multiplexer is switched and conversion is initiated at the same time a 120 pF capacitor should be connected to CEXT to allow for the acquisition time of the track/hold before conversion is initiated. Applications that want to achieve optimum performance from the AD7890 will have to ensure that the data read does not occur during conversion or during 500 ns prior to the rising edge of CONVST. This can be achieved in either of two ways. The first is to ensure in software that the read operation is not initiated until 5.9 s after the rising edge of CONVST. This will only be possible if the software knows when the CONVST command is issued. The second scheme would be to use the CONVST signal as both the conversion start signal and an interrupt signal. The simplest way to do this would be to generate a square wave signal for CONVST with high and low times of 5.9 s (see Figure 4). Conversion is initiated on the rising edge of CONVST. The falling edge of CONVST occurs 5.9 s later and can be used as either an active low or falling edge-triggered interrupt signal to tell the -4- the serial clock signal and the serial data framing signal used for the transfer of data from the AD7890. This selfclocking mode can be used with processors that allow an external device to clock their serial port including most digital signal processors. Interface timing can be obtained from the AD7890 data sheet. processor to read the data from the AD7890. Provided the read operation is completed 500 ns before the rising edge of CONVST, the AD7890 will operate to specification. This scheme limits the throughput rate to 11.8 s minimum. Self-Clocking Mode The AD7890 is configured for its self-clocking mode by tying the SMODE pin of the device to a logic low (LK1 on board in position B). In this mode, the AD7890 provides CONVST SCLK RFS TFS tCONVERT CONVERSION IS INITIATED AND TRACK/HOLD GOES INTO HOLD 500ns MIN CONVERSION ENDS 5.9s LATER SERIAL READ & WRITE OPERATIONS READ & WRITE OPERATIONS SHOULD END 500ns PRIOR TO NEXT RISING EDGE OF CONVST NEXT CONVERSION START COMMAND Figure 3. Control Sequence to Obtain Optimum Performance from the AD7890 CONVST SCLK RFS TFS tCONVERT CONVERSION IS INITIATED AND TRACK/HOLD GOES INTO HOLD 500ns MIN P INT CONVERSION ENDS 5.9s SERVICE OR POLLING LATER ROUTINE SERIAL READ READ & WRITE NEXT CONVST & WRITE OPERATIONS SHOULD RISING EDGE OPERATIONS END 500ns PRIOR TO NEXT RISING EDGE OF CONVST Figure 4. Sequence Using CONVST as an Interrupt Signal -5- Resistors R1, R2, R3, R4 AD780 Voltage Reference IC4, IC5 AD713 Buffer Amplifier IC6 LM78L05 Voltage Regulator IC7 74HC4050 Hex Buffer IC8 74HC125 Quad Bus Buffers with Three State Outputs Capacitors C2, C4, C6, C8, C10 C12, C14 Links LK1, LK2, LK3, LK4, LK5 Sockets SKT1 to SKT13 Subminiature BNC Sockets SKT14 9-Way D Type Connector 10 F Capacitors C1, C3, C5, C7, C9 C11, C13, C15 0.1 F Capacitors C17, C18 0.1 F Capacitors C16 200 pF Capacitor Shorting Plugs E2136-12-5/96 AD7890 IC3 10 k Resistors Figure 5. Silkscreen Layout for Evaluation Board -6- PRINTED IN U.S.A. COMPONENT LIST Integrated Circuits IC1